A. Field of the Invention
This invention relates to the field of digital data processing systems wherein one or more host data processors utilize one or more supporting scientific processors in conjunction with storage systems that are commonly accessible. More particularly, it relates to an improved High Performance Storage Unit for use in such a digital data processing system. Still more particularly, the invention relates to an improved access lock apparatus for use in such a High Performance Storage Unit.
B. State of the Prior Art
Digital data processing systems are known wherein one or more independently operable data processors function with one or more commonly accessible main storage systems. Systems are also known that utilize a support processor with its associated dedicated supporting, or secondary storage system. Such support processors are often configured to perform specialized scientific computations and are commonly under task assignment control of one of the independently operable data processors. The controlling data processor is commonly referred to as a "host processor". The host processor characteristically functions to cause a task to be assigned to the support processor; to cause required instructions and data to be transferred to the secondary storage system; to cause the task execution to be initiated; and to respond to signals indicating the task has been completed, so that results can be transferred to the selected main storage systems. It is also the duty of the host processor to recognize and accommodate conflicts in usage and time that might be detected to exist. Commonly, the host processor is free to perform other data processing matters while the support processor is performing its assigned tasks. It is also common for the host processor to respond to intermediate needs of the support processor, such as providing additional data if required, responding to detected fault conditions and the like.
In the past, support scientific data processors have been associated with host data processing systems. One such prior art scientific processor is disclosed in U.S. Pat. No. 4,101,960, entitled "Scientific Processor" and assigned to Burroughs Corporation, of Detroit, Mich. In that system, a single instruction multiple data processor, which is particularly suited for scientific applications, includes a high level language programmable front-end processor; a parallel task processor with an array memory; a large high speed secondary storage system having a multiplicity of high speed input/output channels commonly coupled to the front-end processor and to the array memory; and an overall control unit. In operation of that system, an entire task is transferred from the front-end processor to the secondary storage system whereupon the task is thereafter executed on the parallel task processor under the supervision of the control unit, thereby freeing the front-end processor to perform general purpose input/output operations and other tasks. Upon parallel task completion, the complete results are transferred back to the front-end processor from the secondary storage system.
It is believed readily seen that the front-end processor used in this earlier system is a large general purpose data processing system which has its own primary storage system. It is from this primary storage system that the entire task is transferred to the secondary storage system. Further, it is believed to be apparent that an input/output path exists to and from the secondary storage system from this front-end processor. Since task transfers involve the use of the input/output path of the front-end processor, it is this input/output path and the transfer of data thereon between the primary and secondary storage systems which becomes the limiting link between the systems. Such a limitation is not unique to the Scientific Processor as disclosed in U.S. Pat. No. 4,101,960. Rather, this input/output path and the transfers of data are generally considered to be the bottleneck in many such earlier known systems.
The present scientific data processing system is considered to overcome the data transfer bottleneck by providing a unique system architecture using a high speed memory unit which is commonly accessible by the host processor and the scientific processor. Further, when multiple high speed storage units are required, a multiple unit adapter is coupled between a plurality of high speed memory units and the scientific processor.
Data processing systems are becoming more and more complex. With the advent of integrated circuit fabrication technology, the cost per gate of logic elements is greatly reduced and the number of gates utilized is ever increasing. A primary goal in architectural design is to improve the throughput of problem solutions. Such architectures often utilize a plurality of processing units in cooperation with one or more multiple port memory systems, whereby portions of the same problem solution may be parcelled out to different processors or different problems may be in the process of solution simultaneously.
The environment in which the apparatus and method of the present invention is used is in the High Performance Storage Unit (HPSU). It is well known that the memory units of such a data processing system often have a plurality of individual requester ports whereby a corresponding plurality of processor units of varying types may seek access via requests to such memory units. It is believed equally well known that where there are pluralities of such requesters seeking simultaneous access to a particular memory unit that there must be some form of a prioritization system. In earlier prioritization systems, it was often the case that once a particular processor unit gains access to a selected memory as a result of its priority, all other requesters are held in abeyance until the requester which has gained access is satisfied and releases the storage unit.
Also, in these earlier systems, these requesters were constantly seeking access to such a memory. Since the stream was a constant one, there were often later requests which had higher priorities than did the earlier ones. In order to have particular groups which could be prioritized at a particular time, there arose a request system known as a "snapshot" system of prioritizing. In a "snapshot" priority scheme, the number of requesters which are attempting communication with the memory unit, will be frozen or snapped into a queue. All of these requesters, in the queue at the time of the "snapshot" will be serviced, in priority order, before any further request will be considered.
Further, any request in the queue which has been already serviced, will not be reinstated. As is obvious, such a scheme is tantamount to the taking of a photograph of the present group of requests, hence, the name "snapshot". This group of preset requests will be serviced prior to taking another "snapshot".
A further priority feature that must be considered in this description is that on the earlier systems, each of the requesters seeking a particular memory port only held its requester line status for a predetermined period of time. Thus, if a plurality of requesters were snapped into a particular queue, all of the requests must be satisfied in a predetermined time period. If the higher priority requests in the queue took an excessive amount of time to be satisfied, then the lower priority requesters timed out. If this happened, then the whole cycle must be repeated since the request could not be satisfied until it was reinstated into some later priority snap.
Another priority feature that it is important to discuss is the scheme called access lock out. In this operation, each port requester gained access to the memory port, it included the further characteristic of being able to prevent any other requester from gaining access. In other words, it locked out access to the memory port so long as the selected requester required the port. Thus, in current systems, the presence of an access lock signal on a port requester would clear all remaining requests in that "snapshot" forcing all pending port requests to be honored during a later priority "snapshot". As discussed, it was possible for this condition to cause the pending requester to time-out before it was honored.
In systems that utilize a multiplicity of processors to access, a common memory system, either for reading or writing, it has been found necessary to establish an access priority sequence between processors seeking access to the memory system. Memory systems that can accommodate multiple requesters, such as multiple processing units, are designated multiple port or multiple channel memory systems. In such systems, it is necessary to identify the processor seeking access to the memory system, and to enable the appropriate port or channel associated with the identified requester. With multiple requesters, it is common to have requests queued up and to have memory addressing and data to be written available for the queued sources. In the event of a decoding error, that is an error in identifying the proper requester, an entirely erroneous selection of addressing and data to be written can occur. Even assuming that parity is associated with the data words, or an ECC system is incorporated, such decoding errors will often go undetected because the word or words processed in the run stream will be proper and correct, but will be associated with the erroneously identified requester. Since the requests are queued, the memory system is essentially pipelined and is conditioned to handle requests in a predetermined manner. Further, through timing control, the operation of the selection and memory system is overlapped. This means that certain functions related with one requester are being completed while other functions of the next subsequent requester are being initiated. It is clear that errors in decoding, that is erroneous identification of requesters, results in system malfunction that is difficult to isolate and identify if not detected close in time to the occurrence of the error condition.